Chips fail as soon as you put them on the machine? Watch me use these six steps to find out the real reason for failure.

Electronic components in the storage, use before the protection measures are not done or not standardized treatment may cause electrostatic damage to the chip, which may affect the service life of the chip or cause the internal circuit breakdown parameter drift and other phenomena, and the serious part of the circuit will cause a direct short-circuit situation.

In this paper, we take the electrostatic damage (ESD) of the chip as an example, and analyze the causes and mechanisms of chip failure through appearance inspection, I-V curve measurement, x-ray inspection, open cover inspection, hot spot analysis, de-lamination analysis and other methods, and put forward suggestions for improvement according to the actual situation.

I. Case background

Feedback from the end-customer on the machine test failure, PCB board can not run normally, cross-validation locked bit A chip is bad, A chip impedance Measurement of the A chip, found that a diode inside the A chip part of the circuit impedance is abnormally low. Now test and analyze to find the cause of failure.

Analysis process

 1. Appearance Inspection

First of all, we check the appearance of A-chip, the chip surface is normal, and we do not find that the chip is damaged, cracked, silkscreen and model inconsistency and other abnormal phenomena.

2. I-V curve measurement

Next, we measured the I-V curve of chip A, and found that the I-V curve of the pins between PIN4 and PIN5 of the sample was short-circuited.

3. X-ray Inspection

Immediately after, we further carried out X-ray inspection on the chip, and did not find any abnormal phenomena such as damage to the internal structure of the chip and bonding line.

4. Open cover inspection

Then, we opened the cover of the chip for inspection, and did not find any obvious traces of damage to the chip.

5.Hot spot analysis

Next, we carried out hot spot analysis, according to the I-V curve check, found that there is a short circuit phenomenon in chip A. In order to confirm the specific location of the short circuit and failure damage point, we used Thermal to hot spot positioning on chip A. From the positioning, it can be seen that there is an abnormal position is in the vicinity of PIN4-PIN5.

6. Delamination analysis

Finally, we performed a delamination analysis based on the location of the hotspot display. By removing layer by layer, we found ESD damage in the CT layer up to the SUB layer, where the damage is the most serious.